Multi-core (computing)

A multi-core microprocessor is one which combines two or more independent processors into a single package, often a single integrated circuit (IC). A dual-core device contains only two independent microprocessors. In general, multi-core microprocessors allow a computing device to exhibit some form of thread-level parallelism (TLP) without including multiple microprocessors in separate physical packages. This form of TLP is often known as chip-level multiprocessing, or CMP.

There is some discrepancy in the semantics by which the terms "multi-core" and "dual-core" are defined. Most commonly they are used to refer to some sort of central processing unit (CPU), but are sometimes also applied to DSPs and SoCs. Additionally, some use these terms only to refer to multi-core microprocessors that are manufactured on the same integrated circuit die. These persons generally prefer to refer to separate microprocessor dies in the same package by another name, such as "multi-chip module", "double core", or even "twin core". This article uses both the terms "multi-core" and "dual-core" to reference microelectronic CPUs manufactured on the same integrated circuit, unless otherwise noted.

Commercial examples

International Business Machines (IBM)'s POWER4, first Dual-Core module processor released in the year 2000
IBM's POWER5 dual-core chip is now in production, and the company has a PowerPC 970MP dual-core processor in production and is in use in the Apple PowerMac G5.
Broadcom SiByte (SB1250, SB1255, SB1455)
PA-RISC (PA-8800)
Sun Microsystems UltraSPARC IV, UltraSPARC IV+, UltraSPARC T1
AMD released its dual-core Opteron server/workstation processors on 22 April 2005, and its dual-core desktop processors, the Athlon 64 X2 family, were released on 31 May 2005. AMD have also recently released the FX-60 and FX-62 for high performance desktop, and Turion 64 X2 for laptop.
Intel's dual-core Xeon processors, code-named Paxville and Dempsey, are shipping at 3 GHz. The company is also currently developing dual-core versions of its Itanium high-end server CPU architecture and produced Pentium D, the dual core version of Pentium 4. A newer chip, the Core Duo, is available in the Apple Computer's iMac, high end Mac mini, MacBook and MacBook Pro, as well as in various laptop PCs, from brands of the likes of Sony, Toshiba, ASUS, and others. The next generation version, Core 2 Duo, codenamed Conroe, is slated for release in July 2006.
Motorola/Freescale has dual-core ICs based on the PowerPC e600 and e700 cores in development.
Microsoft's Xbox 360 game console uses a triple core PowerPC microprocessor.
Raza Microelectronics' XLR processor has eight MIPS cores.
Cavium Networks' Octeon processor has 16 MIPS cores.

Development motivation

Technical pressures

While CMOS manufacturing technology continues to improve, reducing the size of single gates, physical limits of semiconductor-based microelectronics become a major design concern. Some effects of these physical limitations can cause significant heat dissipation and data synchronization problems. The demand for more complex and capable microprocessors causes CPU designers to utilize various methods of increasing performance. Some ILP methods like superscalar pipelining are suitable for many applications, but are inefficient for others that tend to contain difficult-to-predict code. Many applications are better suited to TLP methods, and multiple independent CPUs is one common method used to increase a system's overall TLP. A combination of increased available space due to refined manufacturing processes and the demand for increased TLP led to the logical creation of multi-core CPUs.

Commercial incentives

Several business motives drive the development of dual-core architectures. Since SMP designs have been long implemented using discrete CPUs, the issues regarding implementing the architecture and supporting it in software are well known. Additionally, utilizing a proven processing core design (e.g. Freescale's e700 core) without architectural changes reduces design risk significantly. Finally, the connotations of the terminology "dual-core" (and other multiples) lends itself to marketing efforts.

Additionally, for general-purpose processors, much of the motivation for multi-core processors comes from the increasing difficulty of improving processor performance by increasing the operating frequency (frequency-scaling). In order to continue delivering regular performance improvements for general-purpose processors, manufacturers such as Intel and AMD have turned to multi-core designs, sacrificing lower manufacturing costs for higher performance in some applications and systems.

Multi-core architectures are being developed, but so are the alternatives. An especially strong contender for established markets is to integrate more peripheral functions into the chip.

Advantages

Proximity of multiple CPU cores on the same die have the advantage that the cache coherency circuitry can operate at a much higher clock rate than is possible if the signals have to travel off-chip, so combining equivalent CPUs on a single die significantly improves the performance of cache snoop operations.
Assuming that the die can fit into the package, physically, the multi-core CPU designs require much less Printed Circuit Board (PCB) space than multi-chip SMP designs.
A dual-core processor uses slightly less power than two coupled single-core processors, principally because of the increased power required to drive signals external to the chip and because the smaller silicon process geometry allows the cores to operate at lower voltages; furthermore, the cores share some circuitry, like the L2 cache and the interface to the front side bus (FSB).
In terms of competing technologies for the available silicon die area, multi-core design can make use of proven CPU core library designs and produce a product with lower risk of design error than devising a new wider core design. Also, adding more cache suffers from diminishing returns.

Disadvantages

Multi-core processors do not need the operating system (OS) to support them, but instead adjustments to existing software are required to maximize the computing resources provided by multi-core processors. Also, the ability of multi-core processors to increase application performance depends on using threaded applications to optimize the use of resources.
Integration of a multi-core chip drives production yields down and they are more difficult to manage thermally than lower-density single-chip designs.
From an architectural point of view, ultimately, single CPU designs may make better use of the silicon surface area than multiprocessing cores, so a development commitment to this architecture may carry the risk of obsolescence.

Software impact

Most existing software is not ready to directly utilize the power of multicore processors since they are written in traditional sequential programming languages like C, C++ and FORTRAN, all of which have the limited scope of only one processor in mind.

Current software titles that fully utilize multi-core technologies include: Maya, Blender3D, Quake 3 & 4, Elder Scrolls: Oblivion, 3DS Max, Adobe Photoshop, Windows XP Professional, Windows 2003, Mac OS X, Linux, and many operating systems that are streamlined for server use.

Parallel programming is a must option for a single software to exploit multiple computation units(cores) simultaneously, often by multithread or multitask programming. Some existing parallel programming models such as OpenMP and MPI can be directly used on multi-core platforms. Other research efforts have been seen also, like Cray’s Chapel, Sun’s Fortress, and IBM’s X10.

Concurrency acquires a central role in true parallel application. The basic steps in designing parallel applications are:

Partitioning : The partitioning stage of a design is intended to expose opportunities for parallel execution. Hence, the focus is on defining a large number of small tasks in order to yield what is termed a fine-grained decomposition of a problem.

Communication : The tasks generated by a partition are intended to execute concurrently but cannot, in general, execute independently. The computation to be performed in one task will typically require data associated with another task. Data must then be transferred between tasks so as to allow computation to proceed. This information flow is specified in the communication phase of a design.

Agglomeration : In the third stage, we move from the abstract toward the concrete. We revisit decisions made in the partitioning and communication phases with a view to obtaining an algorithm that will execute efficiently on some class of parallel computer. In particular, we consider whether it is useful to combine, or agglomerate, tasks identified by the partitioning phase, so as to provide a smaller number of tasks, each of greater size. We also determine whether it is worthwhile to replicate data and/or computation.

Mapping : In the fourth and final stage of the parallel algorithm design process, we specify where each task is to execute. This mapping problem does not arise on uniprocessors or on shared-memory computers that provide automatic task scheduling.

On the other hand, on the server side, multicore processors are ideal because they allow many users to connect to a site simultaneously and have independent threads of execution. This allows for Web servers and application servers that have much better throughput.

Licensing

Another issue is the question of software licensing for multi-core CPUs. Typically enterprise server software is licensed "per processor". In the past a CPU was a processor (and moreover most computers had only one CPU) and there was no ambiguity. Now there is the possibility of counting cores as processors and charging a customer for two licenses when they use a dual-core CPU. However, the trend seems to be counting dual-core chips as a single processor as Microsoft, Intel, and AMD support this view. Oracle counts AMD and Intel dual-core CPUs as a single processor but has other numbers for other types. IBM, HP and Microsoft count a multi-chip module as multiple processors. If multi-chip modules counted as one processor then CPU makers would have an incentive to make large expensive multi-chip modules so their customers saved on software licensing. So it seems that the industry is slowly heading towards counting each die (see Integrated circuit) as a processor, no matter how many cores each die has. Intel has released Paxville which is really a multi-chip module but Intel is calling it a dual-core. It is not clear yet how licensing will work for Paxville. This is an unresolved and thorny issue for software companies and customers.

Common Misconceptions

Many people commonly assume that the multithreading benefits of a dual-core processor will translate into a better user experience while multitasking. This is not generally true, as many user applications (such as word processing applications) spend most of their time in an idle state; a person can't switch contexts faster than a computer. The improvements in computer responsiveness are generally a function of the operating system and the application code; many applications are not pervasively multithreaded since coding multithreaded applications is generally considered to be very difficult.

Notes

Digital signal processors, DSPs, have utilized dual-core architectures for much longer than high-end general purpose processors. A typical example of a DSP-specific implementation would be a combination of a RISC CPU and a DSP MPU. This allows for the design of products that require a general purpose processor for user interfaces and a DSP for real-time data processing; this type of design is suited to e.g. mobile phones.
Two types of operating systems are able to utilize a dual-CPU multiprocessor: partitioned multiprocessing and symmetric multiprocessing (SMP). In a partitioned architecture, each CPU boots into separate segments of physical memory and operate independently; in an SMP OS, processors work in a shared space, executing threads within the OS independently.

External links

Computer architecture | Digital signal processing | Microprocessors

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