Context switch

A context switch is the computing process of storing and restoring the state of a CPU (the context) such that multiple processes can share a single CPU resource. The context switch is an essential feature of a multitasking operating system. Context switches are usually computationally intensive and much of the design of operating systems is to optimize the use of context switches. A context switch can mean a register context switch, a task context switch, a thread context switch, or a process context switch. What constitutes the context is determined by the processor and the operating system.

When to switch?

There are several scenarios where a context switch needs to occur.

Multitasking

Most commonly, within some scheduling schema, one process needs to be switched out of the CPU so another process can run. Within a preemptive multitasking operating system, the scheduler allows every task to run for some certain amount of time, called its time slice.

However, if a process does not voluntarily yield the CPU (for example, by performing an I/O operation), a timer interrupt fires, and the operating system schedules another process for execution instead. This ensures that the CPU cannot be monopolized by any one processor-intensive application.

Interrupt handling

Some architectures (like the Intel x86 architecture) are interrupt driven. This means that if the CPU requests data from a disk, for example, it does not need to busy-wait until the read is over, it can issue the request and continue with some other execution; when the read is over, the CPU can be interrupted and presented with the read. For interrupts, a short program called an interrupt handler is installed, and it is the interrupt handler that handles the interrupt from the disk.

Clearly, there is a necessity to switch contexts when issuing interrupts: so that the interrupt handler can be executed, the state of the currently running process must be suspended.

User and kernel mode switching

When a transition between user mode and kernel mode is required in an operating system, a context switch is not necessary; a mode transition is not a context switch.

Context switch: steps

In a context switch, the state of the first process must be saved somehow, so that, when the scheduler gets back to the execution of the first process, it can restore this state and continue normally.

The state of the process includes all the registers that the process may be using, especially the program counter, plus any other operating system specific data that may be necessary. Often, all the data that is necessary for state is stored in one data structure, called a switchframe or a process control block.

Now, in order to switch processes, the switchframe for the first process must be created and saved. The switchframes are sometimes stored upon a per-process stack in kernel memory (as opposed to the user-mode stack), or there may be some specific operating system defined data structure for this information.

Since the operating system has effectively suspended the execution of the first process, it can now load the switchframe and context of the second process. In doing so, the program counter from the switchframe is loaded, and thus execution can continue in the new process.

Software vs hardware context switching

Context switching can be performed primarily by software or hardware. Some processors, like the Intel 80286 and higher CPUs, have hardware support for context switches, by making use of a special data segment designated the Task State Segment or TSS. When a task switch occurs (implicitly due to a CALL instruction, referring to a task gate, or explicitly due to an interrupt or exception) the CPU can automatically load the new state from the TSS. With other tasks performed in hardware, one would expect this to be rather fast; however, mainstream operating systems, including Windows, do not use this feature. This is due mainly to two reasons: that hardware context switching does not save all the registers (only general purpose registers, not floating point registers (although the TS bit is automatically turned on in the MSW or the CR0 register, resulting in a fault when executing floating point instructions, which gives the OS the opportunity to do saving and restoring of the floating point state)), and associated performance issues.

Some architectures contain logic to allow several hardware contexts to exist simultaneously, eliminating the need to store and restore the CPU context to memory on context switch. The extreme case is the barrel processor architecture, which switches between threads of execution on every cycle.

Operating system technology | Concurrent computing