A buck converter is a step-down DC to DC converter. Its design is similar to the step-up boost converter, and like the boost converter is a switched-mode power supply that uses two switches (a transistor and a diode) and an inductor, and optionally a capacitor to buffer the output.

The simplest way to reduce a DC voltage is to use a voltage divider circuit, but voltage dividers waste energy, since they operate by bleeding off excess voltage as heat. A buck converter, on the other hand, can be remarkably efficient (easily up to 95% for integrated circuits,) and self-regulating, making them useful for tasks such as converting the 12-24v typical battery voltage in a laptop down to the several volts needed by the processor.

Circuit operation

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The operation of the buck converter is fairly simple, with an inductor and two switches (usually a transistor and a diode) that control the inductor. It alternates between connecting the inductor to source voltage to store energy in the inductor and discharging the inductor into the load.

Continuous mode

A Buck converter operates in continuous mode if the current through the inductor (I_L) never falls to zero during the commutation cycle. In this mode, the operating principle is described by the chronogram in figure 4:

• When the switch pictured above is closed (On-state, top of figure 2), the voltage across the inductor is $V\_L\; =\; V\_i\; -\; V\_o$. The current through the inductor rises linearly. As the diode is reverse-biased by the voltage source V, no current flows through it;
• When the switch is opened (off state, bottom of figure 2), the diode is forward biased. The voltage across the inductor is $V\_L\; =\; -V\_o$ (neglecting diode drop). The current I_L decreases.

The energy stored in inductor L is

$E=\backslash frac\{1\}\{2\}L\backslash times\; I\_L^2$

Therefore, it can be seen that the energy stored in L increases during On-time (as I_L increases) and then decrease during the Off-state. L is used to transfer energy from the input to the output of the converter.

The rate of change of the I_L is given by:

$V\_L=L\backslash frac\{dI\_L\}\{dt\}$

With V_L equal to $V\_i-V\_o$ during the On-state and to $-V\_o$ during the Off-state. Therefore, the increase in current during the On-state is given by:

$\backslash Delta\; I\_\{L\_\{on\}\}=\backslash int\_0^\{t\_\{on\}\}dI\_L=\backslash int\_0^\{t\_\{on\}\}\backslash frac\{V\_L\}\{L\}\backslash ,\; dt=\backslash frac\{\backslash left(V\_i-V\_o\backslash right)\backslash cdot\; t\_\{on\}\}\{L\}$

Identically, the decrease in current during the Off-state is given by: $\backslash Delta\; I\_\{L\_\{off\}\}=\backslash int\_0^\{t\_\{off\}\}dI\_L=\backslash int\_0^\{t\_\{off\}\}\backslash frac\{V\_L\}\{L\}\backslash ,\; dt=-\backslash frac\{V\_o\backslash cdot\; t\_\{off\}\}\{L\}$

If we assume that the converter operates in steady state, the energy stored in each component at the end of a commutation cycle T is equal to that at the beginning of the cycle. That means that the current I_L is the same at t=0 and at t=T (see figure 4).

Therefore, $\backslash Delta\; I\_\{L\_\{on\}\}+\backslash Delta\; I\_\{L\_\{off\}\}=0$

So we can write from the above equations:

$\backslash frac\{\backslash left(V\_i-V\_o\backslash right)\backslash cdot\; t\_\{on\}\}\{L\}-\backslash frac\{V\_o\backslash cdot\; t\_\{off\}\}\{L\}=0$

It is worth noting that the above integrations can be done graphically: In figure 4, $\backslash Delta\; I\_\{L\_\{on\}\}$ is proportional to the surface of the yellow area, and $\backslash Delta\; I\_\{L\_\{off\}\}$ to the surface of the orange area, as these surfaces are defined by the inductor voltage (red) curve. As these area are simple rectangles, their surfaces can be found out easily: $t\_\{on\}\backslash times\; \backslash left(\; V\_i-V\_o\backslash right)$ for each yellow rectangle and $-t\_\{on\}\backslash times\; V\_o$ for the orange one. For the sake of steady state operation, the sum of both surface must be zero.

As can be seen on figure 4, $t\_\{on\}=D\backslash cdot\; T$ and $t\_\{off\}=T-D\backslash cdot\; T$. D is a scalar called the duty cycle with a value between 0 and 1. This yields:

$\backslash left(V\_i-V\_o\backslash right)\backslash cdot\; D\; \backslash cdot\; T\; -V\_o\; \backslash cdot\; \backslash left(T-D\backslash cdot\; T\backslash right)=0$

This equation above can be rewritten as: $V\_o=D\backslash cdot\; V\_i$

From this equation, it can be seen that the output voltage of the converter varies linearly with the duty cycle for a given input voltage. As the duty cycle D is equal to the ratio between t_On and the period T, it cannot be more than 1. Therefore, $V\_o\; \backslash leq\; V\_i$. This is why this converter is referred to as step-down converter.

So, for example, stepping 12v down to 3v (output voltage equal to a fourth of the input voltage) would require a duty cycle of 25%, in our theoretically ideal circuit.

Discontinuous mode

In some cases, the amount of energy required by the load is small enough to be transferred in a time lower than the whole commutation period. In this case, the current through the inductor falls to zero during part of the period. The only difference in the principle described above is that the inductor is completely discharged at the end of the commutation cycle (see figure 5). This has, however, some effect on the previous equations.

We still consider that the converter operates in steady state. Therefore, the energy in the inductor is the same at the beginning and at the end of the cycle (in the case of discontinuous mode, it is zero). This means that the average value of the inductor voltage (V_L) is zero, i.e that the area of the yellow and orange rectangles in figure 5 are the same. This yields:

$\backslash left(V\_i-V\_o\backslash right)D\backslash cdot\; T-V\_o\backslash cdot\; \backslash delta\backslash cdot\; T=0$

So the value of δ is:

$\backslash delta=\backslash frac\{V\_i-V\_o\}\{V\_o\}D$

The output current delivered to the load ($I\_o$) is constant, as we consider that the output capacitor is large enough to maintain a constant voltage across its terminals during a commutation cycle. This implies that the current flowing through the capacitor as a zero average value. Therefore, we have :

$\backslash bar\{I\_L\}=I\_o$

Where $\backslash bar\{I\_L\}$ is the average value of the inductor current. As can be seen in figure 5, the inductor current waveform has a triangular shape. Therefore, the average value of I_L can be sorted out geometrically as follow:

$\backslash bar\{I\_L\}=\backslash left(\backslash frac\{1\}\{2\}I\_\{L\_\{max\}\}\backslash cdot\; D\backslash cdot\; T+\backslash frac\{1\}\{2\}I\_\{L\_\{max\}\}\backslash cdot\; \backslash delta\backslash cdot\; T\backslash right)\backslash frac\{1\}\{T\}=\backslash frac\{I\_\{L\_\{max\}\}\backslash left(D+\backslash delta\backslash right)\}\{2\}=I\_o$

The inductor current is zero at the beginning and rises during t_On up to I_Lmax. That means that I_Lmax is equal to:

$I\_\{L\_\{Max\}\}=\backslash frac\{V\_i-V\_o\}\{L\}D\backslash cdot\; T$

Substituting the value of I_Lmax in the previous equation leads to:

$I\_o=\backslash frac\{\backslash left(V\_i-V\_o\backslash right)D\backslash cdot\; T\backslash left(D+\backslash delta\backslash right)\}\{2L\}$

And substituting δ by the expression given above yields:

$I\_o=\backslash frac\{\backslash left(V\_i-V\_o\backslash right)D\backslash cdot\; T\backslash left(D+\backslash frac\{V\_i-V\_o\}\{V\_o\}D\backslash right)\}\{2L\}$

This latter expression can be written as:

$V\_o=V\_i\backslash frac\{1\}\{\backslash frac\{2L\backslash cdot\; I\_o\}\{D^2\backslash cdot\; V\_i\backslash cdot\; T\}+1\}$

It can be seen that the output voltage of a Buck converter operating in discontinuous mode is much more complicated than its counterpart of the continuous mode. Furthermore, the output voltage is now a function not only of the input voltage (V_i) and the duty cycle D, but also of the inductor value (L), the commutation period (T) and the output current (I_o).

From discontinuous to continuous mode (and vice versa)

As told at the beginning of this section, the converter operates in discontinuous mode when low current is drawn by the load, and in continuous mode at higher load current levels. The limit between discontinuous and continuous modes is reached when the inductor current falls to zero exactly at the end of the commutation cycle. with the notations of figure 5, this corresponds to :

$D\backslash cdot\; T\; +\; \backslash delta\; \backslash cdot\; T=T$

$D\; +\; \backslash delta\; =\; 1$

Therefore, the output current (equal to the average inductor current) at the limit between discontinuous and continuous modes is (see above):

$I\_\{o\_\{lim\}\}=\backslash frac\{I\_\{L\_\{max\}\}\backslash left(D+\backslash delta\backslash right)\}\{2\}=\backslash frac\{I\_\{L\_\{max\}\}\}\{2\}$

Substituting I_Lmax by its value:

$I\_\{o\_\{lim\}\}=\backslash frac\{V\_i-V\_o\}\{2L\}D\backslash cdot\; T$

On the limit between the two modes, the output voltage obeys both the expressions given respectively in the continuous and the discontinuous sections. In particular, the former is

$V\_o=D\backslash cdot\; V\_i=$

So I_olim can be written as:

$I\_\{o\_\{lim\}\}=\backslash frac\{V\_i\backslash left(1-D\backslash right)\}\{2L\}D\backslash cdot\; T$

Let's now introduce two more notations:

• the normalized voltage, defined by $\backslash left|V\_o\backslash right|=\backslash frac\{V\_o\}\{V\_i\}$. It is zero when $V\_o=0$, and 1 when $V\_i=V\_o$;
• the normalized current, defined by $\backslash left|I\_o\backslash right|=\backslash frac\{L\}\{T\backslash cdot\; V\_i\}I\_o$. The term $\backslash frac\{T\backslash cdot\; V\_i\}\{L\}$ is equal to the maximum increase of the inductor current during a cycle, i.e the increase of the inductor current with a duty cycle D=1. So, in steady state operation of the converter, this means that $\backslash left|I\_o\backslash right|$ equals 0 for no output current, and 1 for the maximum current the converter can deliver.

Using these notations, we have:

• in continuous mode, $\backslash left|V\_o\backslash right|=D$
• in discontinuous mode, $\backslash left|V\_o\backslash right|=\backslash frac\{1\}\{\backslash frac\{2L\backslash cdot\; I\_o\}\{D^2\backslash cdot\; V\_i\backslash cdot\; T\}+1\}=\backslash frac\{1\}\{\backslash frac\{2\backslash left|I\_o\backslash right|\}\{D^2\}+1\}=\backslash frac\{D^2\}\{2\backslash left|I\_o\backslash right|+D^2\}$;
• the current at the limit between continuous and discontinuous mode is $I\_\{o\_\{lim\}\}=\backslash frac\{V\_i\backslash left(1-D\backslash right)\}\{2L\}D\backslash cdot\; T=\backslash frac\{I\_\{o\_\{lim\}\}\}\{\backslash left|I\_o\backslash right|\}\backslash cdot\; \backslash frac\{\backslash left(1-D\backslash right)D\}\{2\}$. Therefore, the locus of the limit between continuous and discontinuous modes is given by $\backslash frac\{\backslash left(1-D\backslash right)D\}\{2\backslash left|I\_o\backslash right|\}=1$.

These expression have been plotted in figure 6. From this, it is obvious that in continuous mode, the output voltage does only depend on the duty cycle, whereas it is far more complex in the discontinuous mode. This is important from a control point of view

Non ideal circuit

The previous study was conducted with the following assumptions:

• The output capacitor has enough capacitance to supply power to the load (a simple resistance) without any noticeable variation in its voltage.
• The voltage drop across the diode when forward biased is zero
• No commutation losses in the switch nor in the diode

These assumptions can be fairly far from reality, and the imperfections of the real components can have a detrimental effect on the operation of the converter.

Output Voltage Ripple

Ouput voltage ripple is the name given to the phenomenon where the output voltage rises during the On-state and falls during the Off-state. Several factors contribute to this including, but not limited to, switching frequency, output capacitance, inductor, load and any current limiting features of the control circuitry. At the most basic level the output voltage will rise and fall as a result of the output capacitor charging and discharging:

$dV\_\{o\}\; =\backslash frac\{i\backslash cdot\; dT\}\{C\}$

During the Off-state, the current in this equation is the load current. In the On-state the current is the difference bewteen the switch current (or source current) and the load current. The duration of time (dT) is defined by the duty cycle and by the switching frequency.

For the On-state:

$dT\_\{on\}\; =\; D\; \backslash cdot\; T\; =\; \backslash frac\{D\}\{f\}$

For the Off-state:

$dT\_\{off\}\; =\; (1-D)\; \backslash cdot\; T\; =\; \backslash frac\{1-D\}\{f\}$

Qualitatively, as the output capacitor or switching frequency increase, the magnitude of the ripple decreases. Output voltage ripple is typically a design specification for the power supply and is selected based on several factors. Capacitor selection is normally determined based on cost, physical size and non-idealities of various capacitor types. Switching frequency selection is typically determined based on efficiency requirements, which tends to decrease at higher operating frequencies, as described below in Effects of non-ideality on the efficiency. Higher switching frequency can also reduce efficiency and possibly raise EMI concerns.

Output voltage ripple is one of the disadvantages of a switching power supply, and can also be a measure of its quality.

Effects of non-ideality on the efficiency

A simplified analysis of the buck converter, as described above, does not account for non-idealities of the circuit components. These non-idealities account for all the power losses in the circuit.

Both static and dynamic power losses occur in any switching regulator. Static power losses include $I^2R$ (conduction) losses in the wires or PCB traces, as well as in the switches and inductor, as in any electrical circuit. Dynamic power losses occur as a result of switching, such as the charging and discharging of the switch gate, and are proportional to the switching frequency.

It is useful to begin by calculating the duty cycle for a non-ideal buck converter, which is:

$D\; =\; \backslash frac\{V\_o+(V\_\{SWITCH\}\; +\; V\_L)\}\{V\_i\; +\; V\_\{SYNCHSW\}\; -\; V\_\{SWITCH\}\; -\; V\_L\}$

where:

V_SWITCH is the voltage drop on the power switch, V_SYNCHSW is the voltage drop on the synchronous switch or diode, and V_L is the voltage drop on the inductor.

The voltage drops described above are all static power losses which are dependent primarily on DC current, and can therefore be easily calculated. For a transistor in saturation or a diode drop, V_SWITCH and V_SYNCHSW may already be known, based on the properties of the selected device.

$V\_\{SWITCH\}\; =\; I\_\{SWITCH\}\; \backslash cdot\; R\_\{ON\}\; =\; D\; \backslash cdot\; I\_o\backslash cdot\; R\_\{ON\}$
$V\_\{SYNCHSW\}\; =\; I\_\{SYNCHSW\}\; \backslash cdot\; R\_\{ON\}\; =\; (1-D)\; \backslash cdot\; I\_o\; \backslash cdot\; R\_\{ON\}$
$V\_L\; =\; I\_L\backslash cdot\; R\_\{DCR\}$

where:

R_ON is the ON-resistance of each switch (RDSON for a MOSFET), and R_DCR is the DC resistance of the inductor.

The careful reader will note that the duty cycle equation is somewhat recursive. A rough analysis can be made by first calculating the values V_SWITCH and V_SYNCHSW using the ideal duty cycle equation.

Switch resistance, for components such as the Power MOSFET, and forward voltage, for components such as the Insulated Gate Bipolar Transistor (IGBT) can be determined by referring to datasheet specifications.

In addition, power loss occurs as a result of leakage currents. This power loss is simply

$P\_\{LEAKAGE\}\; =\; I\_\{LEAKAGE\}\; \backslash cdot\; V$

where:

I_LEAKAGE is the leakage current of the switch, and V is the voltage across the switch.

Dynamic power losses are due to the switching behavior of the selected pass devices (MOSFETs, Power Transistors, IGBTs, etc.). These losses include turn-on and turn-off switching losses and switch transition losses.

Switch turn-on and turn-off losses are easily lumped together as

$P\_\{SW\}\; =\; \backslash frac\; \{V\; \backslash cdot\; I\_o\; \backslash cdot\; (t\_\{RISE\}\; +\; t\_\{FALL\})\}\; \{6\; \backslash cdot\; T\}$

where:

V is the voltage across the switch while the switch is off, t_RISE and t_FALL are the switch rise and fall times, and T is the switching period.

When a MOSFET is used for the lower switch, additional losses may occur during the time between the turn-off of the high-side switch and the turn-on of the low-side switch, when the body diode of the low-side MOSFET conducts the output current. This time, known as the non-overlap time, prevents "shootthrough," a condition in which both switches are simultaneously turned on. The onset of shootthrough generates severe power loss and heat. Proper selection of non-overlap time must balance the risk of shootthrough with the increased power loss caused by conduction of the body diode.

Power loss on the body diode is also proportional to switching frequency and is

$P\_\{BODYDIODE\}\; =\; V\_F\; \backslash cdot\; I\_o\; \backslash cdot\; t\_\{NO\}\; \backslash cdot\; f\_\{SW\}$

where:

V_F is the forward voltage of the body diode, and t_NO is the selected non-overlap time.

Finally, power losses occur as a result of the power required to turn the switches on and off. For MOSFET switches, these losses are dominated by the gate charge, essentially the energy required to charge and discharge the capacitance of the MOSFET gate between the threshold voltage and the selected gate voltage. These switch transition losses occur primarily in the gate driver, and can be minimized by selecting MOSFETs with low gate charge, by driving the MOSFET gate to a lower voltage (at the cost of increased MOSFET conduction losses), or by operating at a lower frequency.

$P\_\{GATEDRIVE\}\; =\; Q\_G\; \backslash cdot\; V\_G\; \backslash cdot\; f\_\{SW\}$

where:

Q_G is the gate charge of the selected MOSFET, and V_G is the peak gate voltage with respect to ground.

It is essential to remember that, for N-MOSFETs, the high-side switch must be driven to a higher voltage than V_i. Therefore V_G will nearly always be different for the high-side and low-side switches.

A complete design for a buck converter includes a tradeoff analysis of the various power losses. Designers balance these losses according to the expected uses of the finished design. A converter expected to have a low switching frequency does not require switches with low gate transition losses; a converter operating at a high duty cycle requires a low-side switch with low conduction losses.

Specific structures

multi-phase buck

Low-output voltage buck converters are commonly used in computers to convert the voltage from the power supply to a lower voltage (around 1 V), suitable for the CPU. Such a low voltage means that the allowed value of the voltage ripple (caused by the switching operation of the buck converter) is very low.

To reduce the voltage ripple, it is possible to increase the switching frequency of the converter or, to a lesser extend, to increase the value of the output capacitor or the inductor. Another solution is to use several converters connected in parallel. This structure, called a multi-phase buck uses up to 4 elementary buck converters connected to the same input and output capacitors, with shifted drive signalsGuy Séguier, Électronique de puissance, 7^th edition, Dunod, Paris 1999 (in french).

synchronous rectification

See also

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Boost Converter

Buck-Boost Converter

General DC-DC converters

External links

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• DC-DC Converter Basics Detailed article on DC-DC converters which gives a more formal and detailed analysis of the Buck including the effects of non-ideal switching.
• High Efficiency 2MHz PWM Buck Converter An example of an integrated-circuit Buck converter.

Many Java applets demonstrating the operation of converters are available on the Interactive Power Electronics Seminar (iPES)

References

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Power supplies | Power electronics

Tiefsetzsteller | Convertisseur Buck