Xeon

The Xeon is Intel's name for its server-class PC microprocessors intended for multiple-processor machines. The name has been kept over several generations of processors. Older models added the name Xeon to the end of the name of the corresponding standard range but the more recent models have just used the name Xeon on its own. Xeon chips generally have more cache and support larger multiprocessor configurations than their desktop counterparts.

Pentium II Xeon

The first Xeon processor was released in 1998 as the Pentium II Xeon as the replacement of the Pentium Pro. The Pentium II Xeon was based on the P6 microarchitecture and used either a 440GX (a dual-processor workstation chipset) or 450NX (quad-processor, or oct with additional logic) chipset, and differed from the desktop Pentium II in that it had a full-speed, off-die L2 cache. It also used a larger slot known as slot 2 Cache sizes were 512 KiB, 1 MiB and 2 MiB, and it used a 100 MT/s bus.

Pentium III Xeon

In 1999, the Pentium II Xeon was replaced by the Pentium III Xeon. The initial version (Tanner) was no different from its predecessor, save the addition of SSE and a few cache controller enhancements found in the Pentium III. The second version (Cascades) was somewhat more controversial, in that while it had a 133 MT/s bus it only had a 256 KiB on-die L2 cache - in other words, there was no difference between it and the desktop Pentium III. In order to remedy the situation somewhat, Intel released a second version (also called Cascades, but often suffixed to Cascades 2 MiB to differentiate between it and the 256 KiB version) that came in two variants: with 1 MiB or 2 MiB of L2 cache. The bus speed on these models was fixed at 100 MT/s, though in practice the cache was able to offset this.

Xeon & Xeon MP (32-bit)

The Xeon (dropping "Pentium" from the name) was introduced in mid-2001. The initial variant that used the new NetBurst architecture, Foster, was slightly different from the desktop Pentium 4. It served as a decent workstation chip, but it was almost always outperformed in server applications by the older Cascade 2 MiB core and AMD's Athlon MP. Combined with the need to use expensive Rambus Dynamic RAM (RDRAM), the Foster's sales were somewhat unimpressive.

Foster only supported 2 processors, so a second version (Foster MP) was introduced with a 1 MiB L3 cache. This improved performance slightly, but not by enough to lift it out of third place. It was also much more expensive than the dual-processor (DP) versions.

In 2002 a 130 nm version of the Xeon (this time codenamed Prestonia) was released, now supporting Intel's new Hyper-Threading technology and having a 512 KiB L2 cache. A new server chipset, E7500 (which allowed the use of dual-channel DDR SDRAM) was released to support this processor in servers, and shortly afterwards the bus speed was boosted to 533 MT/s (accompanied by new chipsets; the E7501 for servers and the E7505 for workstations). The new Xeon performed much better than its predecessor and noticeably better than Athlon MP. The support of new features in the E75xx series also gave it a key advantage over the Pentium III Xeon and Athlon MP (both stuck with rather old chipsets), and it quickly became the top-selling server/workstation processor.

The Xeon MP version of the Prestonia was the Gallatin, which had an L3 cache of 1 MiB or 2 MiB. This version also performed a lot better than Foster MP, and was popular in servers. Later on, Intel's experience with the 130 nm process allowed them to port the Xeon over to the Gallatin core and also allowed a Xeon MP with 4 MiB cache.

Xeon & Xeon MP (64-bit)

Due to a severe lack of success with Intel's Itanium and Itanium 2 processors, the 90 nm version of the Pentium 4 (Prescott) was built with support for 64-bit instructions (called EM64T by Intel, though it was much the same as AMD's AMD64 instruction set), and a Xeon version codenamed Nocona was released in 2004. Released with it were the E7525 (workstation), E7520 and E7320 (both server) chipsets, which added support for PCI Express, DDR-II and Serial ATA. Generally speaking the Xeon was noticeably slower than AMD's Opteron, though it could also be much faster in situations where Hyper-Threading came into play.

A slightly updated core called Irwindale was released in early 2005, differing from Nocona in having twice the L2 cache and the ability to reduce its clockspeeds in situations that didn't need much processing power. However, performance numbers generated though independent tests which have been conducted show the Irwindale is still outperformed by the AMD Opteron processor.

64-bit Xeon MPs were introduced in April 2005. The cheaper version was Cranford, an MP version of Nocona. The more expensive version was Potomac; a Cranford with 8 MiB of L3 cache.

Dual-Core Xeon

Intel released the first Dual-Core Xeon, codenamed Paxville DP, on 10 October 2005. Paxville DP is a dual-core version of Irwindale, with 4 MiB of L2 Cache (2 MiB per core). The one Paxville DP model that has been released runs at 2.8 GHz and features an 800 MT/s front side bus.

An MP-capable version, codenamed Paxville MP, has been released on 1 November 2005. There are two versions: one with 2 MiB of L2 Cache (1 MiB per core), and one with 4 MiB of L2 (2 MiB per core). Paxville MP is called the Dual-Core Xeon 7000-series. Paxville MP ranges between 2.67 and 3.0 GHz (model numbers 7020-7041), with some models having a 667 MT/s FSB, and others having an 800 MT/s FSB.

Dual-Core Xeon LV

On 14 March 2006, Intel released the processor codenamed Sossaman as the Dual-Core Xeon LV. Sossaman is a low-power, ultradense environment, dual-processor capable chip based on the Core Duo processor technology. As such, it supports the same feature set as current Xeons, Virtualization Technology, 667 MT/s front side bus, and dual-core processing but with 32-bit support only.

Dual-Core Xeon (65 nm NetBurst)

On 23 May 2006, Intel released the Dual-Core Xeon codenamed Dempsey. Released as the Dual-Core Xeon 5000-series, Dempsey is a NetBurst processor built on a 65 nm process, and is virtually identical to Intel's "Presler" Pentium Extreme Edition, except for SMP support, which lets Dempsey operate in dual-processor systems. Dempsey ranges between 2.67 and 3.73 GHz (model numbers 5030-5080). Some models have a 667 MT/s FSB, and others have a 1066 MT/s FSB. Dempsey has 4 MiB of L2 Cache (2 MiB per core). A Medium Voltage model, at 3.2 GHz and 1066 MT/s FSB (model number 5063), has also been released. Dempsey also introduces a new interface for Xeon processors: Socket J, also known as LGA 771.

Dual-Core Xeon (65 nm Intel Core Microarchitecture)

On 26 June 2006, Intel released the Dual-Core Xeon codenamed Woodcrest; it is the first Intel Core Microarchitecture processor to be launched on the market. It is a server and workstation version of the Intel Core 2 processor. Intel claims that it provides an 80% boost in performance, while reducing power consumption by 20% relative to the Pentium D.

It has a 1333 MT/s FSB in most models, except for the 5110 and 5120, which have a 1066 MT/s FSB, with the fastest processor clocking in at 3.0 GHz. All Woodcrests use LGA 771 and all but the 5160 and 5148LV have a TDP of 65 W, which is much less than the previous generation of 130 W. The 5160 has a TDP of 80W, still much less than 130W, and the 5148LV, which will be available in Q3 2006, has a TDP of 40W. All models support EM64T, the XD bit, and Virtualization Technology, with Demand-Based Switching only on Dual-Core Xeon 5140 or above.

Future versions

Tulsa

An improved version of Paxville MP, built on a 65 nm process, with more cache. Tulsa is rumoured to have 2 MiB of L2 (1 MiB per core) and up to 16 MiB of L3 shared between the cores. Will likely use the same LGA 771 interface as Dempsey. Tulsa will be released in two lines: the N-line will use a 667 MT/s FSB, and the M-line will use an 800 MT/s FSB. The N-line will range from 2.5 to 3.33 GHz (model numbers 7110N-7140N), and the M-line will range from 2.6 to 3.4 GHz (model numbers 7110M-7140M). L3 cache will range from 4 MiB to 16 MiB across the models. ^*

Clovertown

A quad-core version of Woodcrest, consisting of two Woodcrest dies on a multi-chip module. Rumoured to use a 1066 MT/s FSB. Intel plans to release Clovertown towards the end of 2006, and the clock speeds will likely be a step or two down from Woodcrest. There will also be an MP-capable version of Clovertown, codenamed Clovertown-MP.

Whitefield

A quad-core processor, partially based on Woodcrest, using the new Common System Interface (CSI) bus, which will be shared with the Itanium 2 processors of its generation (beginning with the "Tukwila" core). Whitefield would have had 16 MiB of L2 cache. and manufactured using the 65 nm process initially, and the 45 nm process later, but it was cancelled from the processor roadmap, and replaced with another processor, codenamed Tigerton. Whitefield was the first full processor being worked on at Whitefield, Bangalore, and hence the name.

Tigerton

A quad-core processor, to be released in place of Whitefield. Other details are unknown at this time.

Dunnington

The 45 nm successor to Tigerton, which is said to be a quad-core processor, but rumours have placed the core count at anywhere from four to thirty-two cores.

Harpertown

Harpertown is said to be a 45 nm, eight-core processor with 12 MiB of L2 cache. An older rumour stated that it was simply the 45 nm shrink of Woodcrest, but that has since changed. Note that the most recent description of Harpertown is very similar to the previously leaked information regarding Dunnington.

Gainestown

Quad-core processor based on Intel's upcoming Nehalem microarchitecture. Rumoured to start at 3.0 GHz.

External links

Xeon Processor at the Intel website
Intel Processors technical specifications at The BalusC Server
Intel Pentium II Xeon and Pentium III Xeon images and descriptions at cpu-collection.de
Hardware Secrets Xeon pages - explains DP and MP

Intel | Microprocessors

x86 microprocessors

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