The StrongARM microprocessor is a faster version of the Advanced RISC Machines ARM design. It was created by Digital Equipment Corporation, but later sold to Intel who continued to manufacture it, before replacing it with the XScale.

History

The StrongARM was a collaborative project between DEC and ARM to create a faster CPU based on (but not totally compatible with) the existing ARM line. The StrongARM was designed to address the upper-end of the low-power embedded market, where users needed more performance than the ARM could deliver while being able to accept more external support. Targets were devices such as newer personal digital assistants and set-top boxes.

The project was set up in 1995, and quickly delivered their first design, the SA-100. This was immediately incorporated into newer versions of the Apple Newton, the Acorn Risc PC, Eidos Optima video editing system, as well as a number of other products.

Digital Semiconductor, DEC's chip division, was later sold to Intel as part of a lawsuit settlement. Intel used the StrongARM to replace their ailing line of RISC processors, the i860 and i960. Today the design has been replaced by the Intel XScale.

Description

The StrongARM family are faster versions of the existing ARM processors with a somewhat different instruction set. Clocked at 206MHz they can perform up to 235 MIPS (1.14 MIPS/MHz). They have limited software compatibility with the "real" ARM families due to their separate caches for data and instructions, which causes self-modifying code to fail. The StrongARM has an "invalidate cache line" instruction to let the CPU know to reload from main memory. This situation arises rarely in typical software however, and StrongARM is certainly not the only processor to have made such a sacrifice. The Motorola 68020, for instance, caused similar compatibility problems for any software designed for the earlier 68000 and 68010 models.

The StrongARM is designed with slow (and therefore cheap and low cost) memory in mind. The StrongARM has a 64 way set associative cache which works on virtual addresses. The high set associativity allows a higher hit rate than competing designs, and the use of virtual addresses allows memory to be simultaneously cached and uncached. A write buffer allows writes to main memory to happen without the CPU stalling, increasing the efficiency of the design.

The SA-100 was the first member of the family, updated as the SA-110 and then SA-1110.

ARM architecture

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