Sinclair ZX81

The Sinclair ZX81 home computer, released by Sinclair Research in 1981, was the follow up to the company's ZX80. The case was black, with a membrane keyboard; the machine's distinctive appearance was the work of industrial designer Rick Dickinson. Video output, as in the ZX80, was to a television set, and saving and loading programs was via an ordinary home audio tape recorder to magnetic audio tapes. It was very significant historically because it was the first home computer under $100 USD (in kit form), and therefore was a big volume seller. A US-only version was produced by Timex as the "Timex Sinclair 1000".

General description

As with the ZX80, the processor was a NEC Zilog Z80-compatible, running at a clock rate of 3.25 MHz. The system board had been redesigned with a custom chip and now had only four or five chips: a Z80A microprocessor, a custom logic chip (Ferranti ULA) or ASIC, a 2364 8Kx8 bit ROM chip, and either one 4118 1Kx8 bit or two 2114 1Kx4 bit RAM chips. The system ROM had grown to 8 KB in size, and the BASIC now supported floating point arithmetic. In the early days, Sinclair offered the ROM as an upgrade for the ZX80.

The base system as supplied (for approximately £70 in the UK or $100 in the US) had 1KB (1024 bytes) of RAM. This RAM was used to hold the computer's system variables, the screen image, and any programs and data. The screen was text only, 32 characters wide by 24 high. However blocky graphics with a resolution of 64 by 48 pixels were possible by the use of the PLOT command, which ingeniously selected among a set of 16 graphics characters. To conserve memory, the screen bytes were stored as minimal length strings: for example, if a screen line was only 12 characters long, it would be stored as only those 12 characters followed by the code for a new line, the rest of the line being automatically assumed to be spaces. Using this knowledge, it was common to write programs that kept to the top left of the screen to save memory. As another memory-saving feature, BASIC keywords were stored as 1-byte tokens. If memory grew short, the number of lines displayed on the TV screen would be reduced.

Even with all these space saving measures the little machine's memory did not go very far, so an expansion pack was available with 16K of RAM ($100 in the US). By mid-1982, 32K and 64K expansion packs were available. These plugged onto the main circuit board (and the 16K Memopak could be "stacked" with a 16K or 32K one) and were notorious for wobbling and losing the results of hours of programming. A printer was marketed to accompany the ZX81: This was a spark printer (although it was sometimes misleadingly called a "thermal printer") in which a wire point sparked the dot pattern into 4-inch-wide silvery-grey aluminised paper, accompanied by a distinct odor of ozone.

Even so, there were many games and applications that run in the minimalistic 1 K, including a basic game of Chess. It was not that hard to get to know, understand, and control the computer completely, something almost impossible today.

There were also an RS-232 serial interface (at ~$140) and a Centronics parallel interface (at ~$105) that would allow the ZX81 to communicate to a standard printer, as well as a full-sized external keyboard (at ~$85).

DK'tronics sold a case and keyboard which, with considerable skill, could be used to replace the membrane keyboard and black "doorstop" case.

In the ZX80 and ZX81, the video output was generated by the Z80 chip. In the ZX80, when a program ran the screen blanked until the program paused again for input. An improvement of the ZX81 over the ZX80 was that the ZX81 had two modes of operation. The ZX81 could run in FAST mode like the ZX80, blanking while programs ran, or in SLOW mode (approximately 1/4 as fast) in which the video was maintained since programs only ran during the blank top and bottom border area of the screen. Since a FOR-NEXT loop from 1 to 1000 took 19 seconds, it was common to run the machine in FAST all the time, even when editing a program, causing the TV to flash every time a key was pressed into the editor.

Another trait of the ZX81 was that it echoed the signal from the tape recorder to the screen whilst loading and saving programs using cassettes, causing the TV to display zigzagging patterns.

The ZX81 did not have the ability to make sound, but by clever coding it was possible to modulate the interference that the processor caused on the TV and create a VERY simple musical keyboard. (Producer Aphex Twin claims he was able to play music on a ZX81 when he had one at the age of 11. ^*)

The ZX81 did not use ASCII but had its own character set. Character code 0 was space, codes 1-10 were used for blocky graphics, codes 11-63 corresponded to punctuation, numbers and upper case characters. Character codes 128-191 were reverse video versions of the first 64 characters. Other codes represented BASIC keywords and control codes such as NEWLINE. There were no lower case characters.

Because the display was generated primarily by software in the ZX81 ROM, it was possible to override the interrupt service routine and generate the display oneself. Several "hi-res" (meaning, 256x192, rather than 64x48) games did this, notably from a company called Software Farm.

There was a notorious bug causing some ZX81s to give the square root of 0.25 as 1.3591409 rather than 0.5. Sinclair's reputation for poor quality control was due less to the existence of the bug in some machines, and more to the time it took to react once the bug had been reported. Conversely, an article in BYTE of the time, comparing mathematical accuracy of several mainstream and much more expensive computers of the time, reflected positively on the ZX81.

The ZX81 sold in large numbers, until it was replaced by its greatly upgraded successor, the ZX Spectrum.

The Sinclair ZX81 was sold in the U.S. by Sinclair itself (from its facility in Nashua, New Hampshire) and also by Timex as the Timex-Sinclair TS1000. The TS1000 shipped with twice as much RAM (2 KB!)

The BASIC interpreter was fully proprietary, unlike most microcomputers of this era (except the original Apple II) which used a series of similar but incompatible Microsoft BASIC variants. This meant that there was no need to comply with ASCII or any other existing standards.

ZX81 internal workings

The technical means used to implement the display and other parts of ZX81 was quite original - at a time when the entire "home" class of computers was in its infancy. The system operated as follows:

Hardware overview

The integrated circuits

The ZX81 contains (depending on RAM type) four or five chips; ROM, CPU, SRAM, and a Ferranti Gate array (or ULA – Uncommitted Logic Array). The ROM occupies addresses 0-8191 (but also addresses 8192-16383, due to minimal decoding hardware). The 1K (or 2K for Timex) SRAM is placed at address 16384 (but repeats up to address 32767). A15 is used for display purposes (see below), and the upper 32K memory area is therefore unusable for code execution. It may still be used to store data, such as BASIC programs or large arrays, however. Unless more than 16K RAM is installed, this upper 32K area is mirroring the lower 32K (except for code execution).

Character display

The computer uses a resizable display-file (screen buffer) meaning that it can be expanded or shrunk depending on the amount of installed memory and the amount of free space at the moment.

There is also a completely non-standard (non-ascii) character set in which 0-63 are printable characters and 128-191 the same characters in reverse video. Bit 6 has special meaning here as, under normal circumstances, the only value with bit 6 set that should be written to the display file is 118, which is a NEWLINE (and also the opcode for HALT!). Placing any other byte with bit 6 set into the display-file would cause unexpected results and may cause the machine to crash.

The ZX81 has the bitmaps (patterns) of the character set stored in the uppermost 512 bytes of its 8K BASIC ROM.

Multiplexing

Resistors function as cheap multiplexers and are placed in series with the data lines (CPU & ULA on one side, ROM & RAM on the other) allowing the ULA to override data when the CPU reads from memory (see below).

There are also resistors in series with address lines A0-A8, separating the ROM and ULA from the CPU (and from any add-on hardware) on those lines; this is used by the ULA to read pixel patterns out of the ROM by overriding address bits A0-A8, while allowing the CPU to control address bits A9-A12 (see below).

The Z80

The conversion of the character codes into pixels on the TV screen employs both well known and other Z80-specific capabilities, most notably the use of the R and I registers:

The register R is intended as a dynamic RAM refresh counter; during the last part of each opcode fetch, the value of this counter is fed onto the lower portion of the address bus, and the RFSH control signal becomes active. However, also the interrupt vector register, I, is output* during the refresh cycles, but on the upper portion of the address bus.

The HALT instruction is also of central importance in the ZX81, it's necessary to know that a halted Z80 executes repeated NOPs until an interrupt occurs, and that these NOPs causes the refresh counter to tick, just as normal NOPs do.

* Undocumented by Zilog and other manufacturers (such as NEC) at the time.

Keyboard scanning

The membrane keyboard is scanned during (and closely coupled to) the vertical retrace interval. The scan patterns is laid out by the upper* eight bits of the unbuffered address bus and read back through five TTL inputs (8x5 = 40). It thus takes eight readings to determine which "keys" are being pressed. Decoding and debounce are done in software.

* This exploits the undocumented feature that (for instance) IN A,(C) actually puts the whole BC register pair on the address bus.

TV picture generation

The I register is normally set to point to the base of the character set bitmap table in ROM. The refresh counter, R, is used to count the 32 character positions on the screen during each scan line (whether or not there are 32 actual characters to display).

During each scan line, the CPU enters a HALT state as soon as it encounters the NEWLINE (HALT) that terminates each line of characters in the display-file. When the R register has counted all 32 positions, a maskable interrupt or INT is generated to bring the processor out of the HALT state, just in time to prepare for another raster line.

SLOW mode

During the upper and lower blank parts of the screen, the computer executes application code (i.e. BASIC or machine code), but a non-maskable interrupt (or NMI) briefly interrupts even this, once every HSYNC period; a counter is updated by the NMI-routine, so it can decide whether it's time to go back and produce character patterns again.

Unfortunately, the use of the SLOW (smooth multitasking mode) slows all other processing by approximately 75% compared to the FAST (flickery mode).

Executing characters

To actually produce a TV raster scan line of 256 pixels, the interrupt routine literally jumps to the start of the currently scanned line of characters in the display file, but with address line A15 set (i.e. 32768 added); the Z80 control line M1 is also active (indicating an opcode-fetch), and this combination is detected by the ULA:

The CPU fetches the character codes (as if it were opcodes), enabling the ULA to easily latch the values; by forcing a NOP (all zeroes) onto the Z80 data bus after each retrived byte, the ULA ensures that "nothing happens" except that the R register keeps track of the character positions on the line, and that the program counter functions as an auto incrementing pointer into the display file.

As long as the retrived data has bit 6 reset (a character), the CPU will continue "executing" characters (as NOPs), helping the ULA reading character codes out of the display file. When the ULA detects the HALT (bit 6 set), it allows the Z80 to execute it normally; the processor stays halted and executes NOPs until the R-register wraps around to zero and thereby generates an INT - this works because INT is hardwired to A6.

This process is repeated eight times for each line of characters, and 192 times for a full TV frame.

The ZX81 makes extensive use of rather intricate "instruction timing", in the ROM program, as well as some small but delicate hardware fixes to fine-tune this system and avoid glitches and jitter in the generated video picture.

=The interrupts

= The INT routines are not proper interrupt routines, in that they mostly do not return. Instead, the return address is constantly discarded so that each interrupt can (technically) "interrupt" the previous, without causing stack overflow. Only once every eight lines is the pushed address used; it then points to the next line of characters in the (possibly) irregular display file, directly after the HALT instruction.

The NMI interrupt, however, always makes traditional "returns" to the application code during (the greater part of) each line in the upper and lower parts of the screen (the borders). However, when it's time to initiate the character pattern display, it turns the NMI generator off, and transfers control to the INT routines (and vice versa).

=More details and timing

= Due to the refresh-mechanism, the Z80 opcode-fetch consists of four clock cycles, which (during generation of eight pixels) are spent as follows:

During the first and second (the opcode fetch), the processor attempts to fetch a character code (as if it were an instruction), but the ULA latches the actual data, while forcing a NOP onto the Z80-bus, as described above.

During the third and fourth (the DRAM refresh) the ULA composes the address to the actual byte of pixel-data; bit 0-5 of the latched code is fed onto bit 3-8 of the ROM address (selecting one of the 64 different character patterns); the interrupt vector register supplies the base address (bit 9-12), while bit 0-3 comes from a modulo 8 counter (in the ULA) clocked by HSYNC and thereby selecting one of the eight pixel-rows for all characters on a line simultaneously.

The byte from the ROM is then fed into a shift-register, controlled by the same "crystal" as the CPU, and clocked out to the TV set at twice the CPU frequency (8 pixels during the 4 cycle NOP).

Syncronization pulses (HSYNC and VSYNC) are output by the ULA and mixed with the video signal such that white=5V, black=2.5V, and SYNC=0V. HSYNC is autonomously generated in hardware, while VSYNC is generated under CPU control in connection with keyboard scanning.

Bit 7 from the original character byte is read by the ULA and controls inverse-video on a per-character basis.

The video sync uses the same individual I/O bit as is used to generate the output for the 250 bit/s cassette recorder interface.

RAM pack & add-ons

Expansion

The lower eight I/O address bits were used as individual chip selects for individual I/O devices within the ULA. Every lower address bit except that selecting the desired device would therefore have to be one, theoretically allowing up to eight I/O devices. In the standard configuration, the only I/O present (unless the optional external ZX printer was plugged into the 40-pin bus edge connector) was one bit for the cassette input, one bit for the cassette/video sync output, a five-bit word of input from the keyboard (a dreadful 40 key device which resembled a car bumper sticker more than it resembled a proper keypad) and whatever control registers were required to enable the ULA itself for video generation. This meant that not all eight bits were used, allowing some limited room for external expansion.

The external RAMpack used eight 4116 chips (a primitive 16 K x 1 bit dynamic RAM in a 16-pin DIP with 1 data pin, 7 multiplexed address pins, /RAS, /CAS, /WE and power). These old chips required +12 V, +5 V and -5 V while the ZX81's internal power supply was merely a 7805 chip (a 5V linear regulator attached to a small metal heatsink which became rather warm as the ZX81 was powered from a 9 V adapter through a 1/8 in (3 mm) phone jack). The RAMpack contained an oscillator and some inductors to invert +5 V to the other required voltages as well as circuitry to multiplex the address lines, adding significantly to its internal complexity.

The 16K external RAM-pack tied the RAM-CS line on the 40 pin edge connector to a constant level to disable the internal RAM.

Unfortunately the 40 pin bus edge connector itself was not gold-plated (the contacts were covered with plain solder) and was very prone to bad connections and oxidation which rendered the upgraded ZX81 system very mechanically fragile and crash-prone. This would become annoying as it would take eight minutes to reload the full 16Kbyte RAM from an (often-unreliable) cassette tape. Home-brew "kludge" solutions to this problem varied from physically bolting the computer and RAMpack to a solid substrate to placing the whole works in a larger case with a proper surplus keyboard in place of the original.

User defined charset and hires

Another less-common upgrade made by some end-users was to connect static RAM (as "pseudo-ROM")in place of the ROM mirrored at addresses 8192-16383. This RAM would need to be connected to the same side of the data bus resistors as the ROM itself so that it could be used to store a user-defined character set of up to 64 characters. One variant on this theme added a one-bit latch to latch the high data bit of the original character (when M1 and A15 were both active) in order to use it to drive one of the address bits, allowing all 128 character bitmaps to be redefined.

As the main RAM was on the wrong side of the data and address bus resistors for this to work, the extra static RAM was required for this approach. Loading the I register to point to the main RAM would not produce the desired result, instead displaying garbage as pixels.

Clones

The ZX81 was cloned for sale outside Europe, with Timex Sinclair, a joint venture, producing the TS1000 for the US market.

The ZX81 was also cloned in the Brazilian Market by many local companies, among them: Apply, Ritas, Microdigital and Prológica (these two being the main competitors for the market). Microdigital produced TK80 (a ZX80 clone), TK82, TK82-C, TK83 and TK85 ^*. Prológica produced NE-Z80 (ZX80 clone), NEZ-8000, CP-200 and CP-200S (late cheaper version).

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