Signal Integrity, for integrated circuits, refers to tools and techniques that ensure the signals on these chips are of sufficient quality for proper operation. Alternatively, Signal Integrity tools attempt to identify and remove effects that cause a design to malfunction due to distortion of the signal waveforms. In ICs, the main cause of signal integrity problems is noise induced by neighboring connections, or crosstalk. In CMOS technologies, this is primarily due to coupling capacitance, but in general it may be caused by mutual inductance, substrate coupling, non-ideal gate operation, and other sources. Induced noise can have many drastic consequences for digital designs:

• it can make the design work incorrectly in some cases, or even fail completely
• it can make the design slower than planned
• it can create yield problems.

The cost of such a failure is very high, and includes photomask costs, engineering costs, and opportunity cost due to delayed product introduction. Therefore electronic design automation tools have been developed to analyze, prevent, and correct these problems.

History

In the early days of VLSI design, digital chip circuit design and layout were manual processes. The use of abstraction and the application of automatic synthesis techniques have since allowed designers to express their designs using high-level languages and apply an automated design process to create very complex designs, ignoring the electrical characteristics of the underlying circuits to a large degree. However, scaling trends (see Moore's law) brought electrical effects back to the forefront in recent technology nodes. With scaling of technology below 0.25 µm, the wire delays have become comparable or even greater than the gate delays. As a result the wire delays needed to be considered to achieve timing closure. In nanometer technologies at 0.13 µm and below, unintended interactions between signals (or noise) became an important consideration for digital design. At these technology nodes, the performance and correctness of a design cannot be assured without considering noise effects.

Overview

In analog circuits, designers are concerned with noise that arise from physical sources, such as thermal noise, flicker noise, and shot noise. These noise sources on the one hand present a lower limit to the smallest signal that can be amplified, and on the other, define an upper limit to the useful amplification.

In digital circuits, noise arises not from fundamental physical sources, but from the operation of the circuit itself, primarily the switching of other signals. Higher interconnect density has led to each net having neighbors that are closer, thus leading to increased coupling capacitance between neighboring nets. As circuits shrink in accordance with Moore's law, several effects have conspired to make noise problems worse:

• To keep resistance tolerable despite decreased width, modern wire geometries are taller in proportion to their spacing. This increases the sidewall capacitance at the expense of capacitance to ground, hence increasing the induced noise voltage (expressed as a fraction of supply voltage).
• Technology scaling has lead to lower threshold voltages, and has also reduced the headroom between threshold and supply voltage, thus reducing noise margin.
• Logic speeds, and clock speeds in particular, have increased significantly, thus leading to faster transition times. These faster transition times are closely linked to higher capacitive cross talk. Also, at such high speeds the inductive properties of the wires come into play especially mutual inductance.

These effects have increased the interactions between signals and decreased the noise immunity of digital CMOS circuits. This has led to noise being a significant problem for digital ICs that must be considered by every digital chip designer prior to tape-out.

Finding Signal Integrity Problems

Typically, a designer would take the following steps for his verification:

• Perform a layout extraction to get the parasitics associated with the layout. Usually Worst-case parasitics and best-case parasitics are extracted and used in the simulations.
• Accurate noise modeling is a must. Create a list of expected noise events, including different types of noise, such as coupling and charge sharing.
• For each noise event, decide how to excite the circuit so that the noise event will occur.
• Create a SPICE (or another circuit simulator) netlist that represents the desired excitation.
• Run SPICE and record the results.
• Analyze the simulation results and decide whether any re-design is required.

Modern signal integrity tools perform all these steps automatically, producing reports that give a design a clean bill of health, or a list of problems that must be fixed.

Fixing Signal Integrity Problems

Once a problem is found, it must be fixed. Typical fixes include:

• Driver upsizing. The victim driving cell is made stronger by upsizing.
• Buffer insertion. In this approach, instead of upsizing the victim driver, a buffer is inserted at an appropriate point in the victim net.
• Aggressor downsizing. This works by increasing the transition time of the attacking net by reducing the strength of its driver.
• Wire Shielding. Shielding of Critical Nets or Clock Nets using GND and VDD shields to reduce the effect of Crosstalk. May lead to routing overhead.
• Routing changes. Routing changes can be very effective in fixing noise problems mainly by reducing the most troublesome coupling capacitances.

Each of these fixes may possibly cause other problems. This type of issue must be addressed as part of design flows and design closure.

References

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• Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, ISBN 0849330963 A survey of the field of electronic design automation. This summary was derived (with permission) from Vol II, Chapter 21, Noise Considerations in Digital ICs, by Vinod Kariat.

Digital electronics | Electronic design automation