Pentium III

The Pentium III is an x86 (more specifically, an i686) architecture microprocessor by Intel, introduced on February 26, 1999. Initial versions were very similar to the earlier Pentium II, the most notable difference being the addition of SSE instructions and the introduction of a controversial serial number which was embedded in the chip during the manufacturing process. As with the Pentium II, there was also a low-end Celeron version and a high-end Xeon version. The Pentium III was eventually superseded by the Pentium 4. An improvement on the Pentium III design is the Pentium M.

Pentium III cores

Katmai

The original version, Katmai, was very similar to the Pentium II (using a 0.25µm fabrication process), the only differences being the introduction of SSE, and an improved L1 cache controller (which was the cause of the minor performance improvements over the latter PIIs). It was first released at speeds of 450 and 500 MHz. Two more versions were released: 550 MHz on May 17, 1999 and 600 MHz on August 2, 1999. On September 27, 1999 Intel released the 533B and 600B running with 533/600 MHz but using a 133 MHz FSB, all others use a 100 MHz FSB.

The Katmai used the same slot based design as the Pentium II but used the newer SECC2 cartridge that allowed direct CPU core contact with the heatsink.

A notable stepping for enthusiasts was SL35D. This version of Katmai was officially rated for 450Mhz, but often contained cache chips for the 600MHz model and thus usually was capable of running at 600MHz.

Coppermine

The second version, Coppermine, had an integrated full-speed 256-bit 256 KiB L2 cache with lower latency, named Advanced Transfer Cache by Intel, which improved performance significantly over Katmai. Under competitive pressure from AMD’s Athlon processor, Intel also re-worked the chip internally, and finally fixed the well known instruction pipeline stalls. The result was a remarkable 30% increase in instruction processing performance per clock.

It was built on a 0.18 μm process. Pentium III Coppermines running at 500, 533, 550, 600, 650, 667, 700, and 733 MHz were first released on October 25, 1999. From December 1999 to May 2000, Intel released Pentium IIIs running at speeds of 750, 800, 850, 866, 900, 933 and 1000 MHz (1 GHz). Both 100 MHz FSB and 133 MHz FSB models were made.

A 1.13 GHz version was released in mid-2000, but famously recalled after a popular hardware review website (Tom's Hardware) proved it was not stable enough to compile the Linux kernel. The problem was traced to the integrated cache, which simply could not operate at speeds above 1 GHz. Intel needed at least six months to resolve this problem and released 1.1 GHz and 1.13 GHz versions in 2001.

A modified version of Coppermine was developed for Microsoft's Xbox game console. The only significant change was that the chip lost half of its L2 cache, dropping it down to 128 KB. Unlike the Celeron Coppermine variant with the same size L2 cache, Xbox's Coppermine core kept all of its 8-way L2 cache associativity from the Pentium III. This meant that the Xbox CPU's L2 cache was more efficient than Celeron's. The Xbox CPU was manufactured onto the same Micro-PGA2 packaging as notebook chips. ^*

Although the codename Coppermine makes it sound as if the chip was fabricated with copper interconnects, Coppermine in fact used aluminum interconnects.

Coppermine-T

This core was supposed to be an intermediate step between Coppermine and Tualatin, with support for lower-voltage system logic present on the latter but core power within previously defined voltage specs of the former so it could work in older system boards. It existed in Intel's processor roadmap in 2000 but was cancelled on the way to production.

Note: Some sources identified Coppermine cD0-stepping (a stepping of processor is similar to the minor version of a software) to be Coppermine-T. This may not be correct because cD0-stepping was merely a revision to the original Coppermine rather than a new core by itself. It was unlikely to have it placed in roadmap as a new core codename.

Tualatin

The third version, Tualatin, was really just a trial for Intel's new 0.13 μm process. As the Pentium 4 had a much bigger die size than the Pentium III, Intel would get more usable Pentium IIIs out of a wafer, and this would allow them to introduce the 0.13 μm Pentium 4 (Northwood) once the process was achieving optimal yields. Tualatin performed quite well, especially in variations which had 512 KiB L2 cache (called the Pentium III-S). The Pentium III-S variant was mainly intended for servers, especially those where power consumption mattered, i.e., thin blade servers.

Pentium III Tualatins were released during 2001 until early 2002 at speeds of 1.0, 1.13, 1.2, 1.26, 1.33 and 1.4 GHz. Intel did not want a repeat of the situation where the performance of a lower priced Celeron rivaled that of the more expensive Pentium II, so Tualatin never ran faster than 1.4 GHz, the introductory clock rate of the Pentium 4. Overclockers discovered as well that 1.4-1.5 GHz with air-cooled temperatures was reaching the limits of the process and so Intel may have also wanted to avoid sacrificing profits with lower yields of a faster chip.

The Tualatin core was named after the Tualatin Valley and Tualatin River in Oregon, where Intel has large manufacturing and design facilities. Tualatins can be visually distinguished from Coppermine-based Pentium IIIs by the metal heatspreader fixed on top of the package.

Pentium III's SSE Implementation

Since Katmai was built in the same 0.25-micrometer process as Pentium II "Deschutes", it had to implement SSE using as little silicon as possible. To achieve this goal, Intel implemented the 128-bit architecture by double-cycling the existing 64-bit data paths and by merging the SIMD-FP multiplier unit with the x87 scalar FPU multiplier into a single unit. To utilize the existing 64-bit data paths, Katmai issues each SIMD-FP instruction as two μops. To compensate partially for implementing only half of SSE’s architectural width, Katmai implements the SIMD-FP adder as a separate unit on the second dispatch port. This organization allows one half of a SIMD multiply and one half of an independent SIMD add to be issued together bringing the peak throughput back to four FLOPS per cycle — at least for code with an even distribution of multiplies and adds.

The problem with Katmai’s method was that the hardware had implemented a different model of parallelism than was implied by the SSE architecture. This set up a code-scheduling dilemma: Should the code be scheduled for Katmai to maximize near-term performance or would it be better to schedule for the architecture in anticipation of a full implementation in a future processor? Intel solved this dilemma by simply not restoring the original conception. SSE programming optimal for Katmai worked generally well on Coppermine and Tualatin. SSE assembly optimized for Pentium III was not optimal for Pentium 4, however.

While the design of Pentium III's SSE was undoubtedly directly related to the need to maintain a strict die size for Katmai, Coppermine and Tualatin were manufactured on significantly smaller processes and could potentially have been equipped with a superior implementation if Intel had not built a 0.25μ Pentium III. A more impressive implementation had to wait until the arrival of Pentium 4.

Core specifications

Katmai (0.25 µm)

L1-Cache: 16 + 16 KiB (Data + Instructions)
L2-Cache: 512 KiB, external chips on CPU module at 50% of CPU-speed
MMX, SSE
Slot 1
Front side bus: 100, 133 MHz
VCore: 2.0V, (600 MHz: 2.05 V)
First release: May 17, 1999
Clockrate: 450-600 MHz
- 100 MHz FSB: 450, 500, 550, 600 MHz
- 133 MHz FSB: 533, 600 MHz (B-models)

Coppermine (0.18 µm)

L1-Cache: 16 + 16 KiB (Data + Instructions)
L2-Cache: 256 KiB, fullspeed
MMX, SSE
Slot 1, Socket 370 (FC-PGA)
Front side bus: 100, 133 MHz
VCore: 1.6V (cA2), 1.65 (cB0), 1.70 (cC0), 1.75 V (cD0, see below)
First release: October 25, 1999
Clockrate: 550 - 1133 MHz
- 100 MHz FSB: 550, 600, 650, 700, 750, 800, 850, 900, 1000, 1100 MHz (E-Models)
- 133 MHz FSB: 533, 600, 667, 733, 800, 866, 933, 1000, 1133 MHz (EB-Models)

Coppermine cD0-stepping or Coppermine-T (0.18 µm)

L1-Cache: 16 + 16 KiB (Data + Instructions)
L2-Cache: 256 KiB, fullspeed
MMX, SSE
Socket 370 (FC-PGA2)
Front side bus: 133 MHz
VCore: 1.75 V
First release: June, 2001
Clockrate: 866, 933, 1000, 1133 MHz

Tualatin (0.13 µm)

L1-Cache: 16 + 16 KiB (Data + Instructions)
L2-Cache: 256 or 512 KiB, fullspeed
MMX, SSE
Socket 370 (FC-PGA2)
Front side bus: 133 MHz
VCore: 1.45, 1.475 V
First release: 2001
Clockrate: 1000 - 1400 MHz
- Pentium III (256 KiB L2-Cache): 1000, 1133, 1200, 1333 MHz
- Pentium III-S (512 KiB L2-Cache): 1133, 1266, 1400 MHz

References

Diefendorff Keith (March 8, 1999). "Pentium III = Pentium II + SSE: Internet SSE Architecture Boosts Multimedia Performance". Microprocessor Report. Volume 13, Number 3.

External links

Intel | x86 microprocessors

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