Intel Core Microarchitecture

This article is about the new Intel microarchitecture previously known as Next Generation Microarchitecture. For Intel processors branded as "Intel Core", such as the 65 nanometre processor codenamed Yonah and its variants, see Intel Core. For the upcoming line of "Intel Core 2" processors using the Intel Core Microarchitecture, see Intel Core 2.

The Intel Core Microarchitecture is a multi-core processor architecture unveiled by Intel in Q1 2006. It is based around an updated version of the Yonah core and will be the latest iteration of the Intel P6 microarchitecture, which traces its history back to the 1995 Pentium Pro. The extreme heat production of NetBurst-based products and the resulting inability to effectively ramp clock speed was the primary reason that Intel abandoned the NetBurst architecture. Core 2 was designed by the team in Haifa, Israel that previously designed the highly successful Pentium M product line.

The architecture features lower power usage than before and is finally competitive with AMD in heat production. It has multiple cores and hardware virtualisation support (marketed as Virtualization Technology), as well as EM64T and SSE4.

The first processors that use this architecture are code-named Merom, Conroe, and Woodcrest; Merom is for mobile computing, Conroe is for desktop systems, and Woodcrest is for servers and workstations. While architectually identical, the three product lines will differ in the socket used, bus speed, and power consumption. Core-based products will not be branded Pentium; Woodcrest-based products form the Xeon 5100 series, while Conroe and Merom-based processors will be labeled as Core 2.

Technology

The Intel Core Microarchitecture is designed from the ground up, but similar to the Pentium M microarchitecture in design philosophy. The pipeline is 14 stages long — less than half of Prescott's, a signature feature of wide order execution cores. Core's execution unit is 4-issues wide, compared to the 3-issue cores of P6, P6-M (Banias, Dothan, and Yonah), and NetBurst microarchitectures. The new architecture is a dual core design with linked L1 cache and shared L2 cache engineered for maximum performance per watt and improved scalability.

One new technology included in the design is Macro-Ops Fusion, which combines two x86 instructions into a single microinstruction. For example, a common code sequence like a compare followed by a conditional jump would become a single micro-op. Other new technologies include 1 cycle throughput (2 cycles previously) of all 128-bit SSE instructions and a new power saving design. All components will run at minimum speed, ramping up speed dynamically as and when needed (similar to AMD's Cool'n'Quiet power-saving technology). This allows the chip to produce less heat, and consume as little power as possible. For Woodcrest, the server and workstation variant, the front side bus runs at 1333 MHz for most Woodcrests and 1066 MHz for the 1.60 and 1.86 GHz Woodcrests. It is targeted to run at 667 MHz for Merom, the mobile variant, though a second wave of Meroms, supporting 800 MHz FSB, is planned. The desktop version is officially slated to use the 1066 MHz bus, with a later possibility of an Extreme Edition CPU with a 1333 MHz bus, and a future budget version with an 800 MHz FSB.

Unfortunately, the FSB might prove to be the weak link in the future, as is a shared bus infrastructure, unlike AMD's Hypertransport. While not so critical in the mobile and desktop segments, this might be the handicap which will prevent Woodcrest from taking performance leadership from AMD Opteron on systems with more than 2 sockets. Intel attempted to alleviate this problem by the use of advanced prefetchers and memory-disambiguation which try to hide main-memory-access latency.

Intel claims that the power consumption of these new processors to be extremely low — average use energy consumption is to be in the 1-2 watt range in ultra low voltage variants, with Thermal Design Points (TDPs) of 65 watts for Conroe and most Woodcrests, 80 watts for the 3.0 GHz Woodcrest, and 40 watts for the low-voltage Woodcrest. However, this is subject to change. In comparison, an AMD Opteron 875HE processor consumes 55 watts, while the new Energy Efficient Socket AM2 line fits in the 35 watt thermal envelope. Merom, the mobile variant, is listed at 35 watts TDP for standard versions and 5 watts TDP for Ultra Low Voltage (ULV) versions.

Previously, Intel warned that it would now focus on power efficiency, rather than raw performance. However, at IDF, Intel advertised both. Some of the promised numbers are:

20% more performance for Merom at the same power level (compared to Core Duo)
40% more performance for Conroe at 40% less power (compared to Pentium D)
80% more performance for Woodcrest at 35% less power (compared to the original dual-core Xeon)

Road map

Laptops

Merom, first eighth-generation notebook chip, 65 nm, dual-core, 2–4 MiB L2 cache (To be released August 2006)
Penryn, dual-core, 45 nm shrink of Merom, 3–6 MiB L2
Perryville, single-core, 45 nm mobile and desktop processor, 2 MiB L2

Desktops

Conroe, first eighth-generation desktop chip, 65 nm, dual-core, 4 MiB L2 cache (Released July 14, 2006)
- Allendale, dual-core, cut-down Conroe with 2 MiB L2
  - Millville, single-core, cut-down Allendale with 1 MiB L2
  - Wolfdale, dual-core, 45 nm shrink of Allendale, with 3 MiB L2
- Kentsfield, quad-core MCM, consists of two Conroes, with 2 × 4 MiB L2 (8 MiB L2)
  - Yorkfield, eight-core MCM, 45 nm, 12 MiB L2, successor to Kentsfield
- Ridgefield, dual-core, 45 nm shrink of Conroe, with 6 MiB L2
Perryville, single-core, 45 nm mobile and desktop processor, 2 MiB L2

Servers and workstations

Woodcrest, first eighth-generation server and workstation chip, 65 nm, dual-core, 4 MiB L2 cache (Released on June 26, 2006)
Clovertown, quad-core MCM, consists of two Woodcrests, with 2 × 4 MiB L2
Tigerton, quad-core MCM. MP-capable version of Clovertown.
Harpertown, either a dual-core, 45 nm shrink of Woodcrest, or an eight-core, 45 nm MCM with 12 MiB L2
Dunnington, four to thirty-two cores, successor to Tigerton

References

Intel | X86 microprocessors

Intel Core Mikroarchitektur | Intel P8 | Intel Core Microarchitecture | Intel Core微處理器架構