IBM 7030

The IBM 7030, also known as Stretch, was IBM's first attempt at building a supercomputer. The first 7030 was delivered to Los Alamos in 1961.

Originally priced at $13.5 million, its failure to meet its aggressive performance estimates forced the price to be dropped to only $7.78 million and its withdrawal from sales to customers beyond those having already negotiated contracts. Even though the 7030 was much slower than expected, the 7030 was the fastest computer in the world from 1961 until 1964.

Development history

Dr. Edward Teller at the University of California Radiation Laboratory in Livermore, California wanted a new scientific system for three-dimensional hydrodynamic calculations. Proposals were requested for this new system, to be called Livermore Automatic Reaction Calculator or LARC, from both IBM and UNIVAC. Expected to cost roughly $2.5 million and running at one to two MIPS, delivery was to be two to three years after the contract was signed.

At IBM, a small team at Poughkeepsie including John Griffith and Gene Amdahl worked on the design proposal. Just after they finished and were about to present the proposal, Ralph Palmer stopped them and said, "It's a mistake." The proposed design would have been built with either point-contact transistors or surface barrier transistors, both likely to be soon outperformed by the then newly invented diffusion transistors. The team showed Livermore the proposed design to illustrate the kind of system IBM was capable of building but said, "We are not going to build that machine for you; we want to build something better! We do not know precisely what it will take but we think it will be another million dollars and another year, and we do not know how fast it will run but we would like to shoot for ten million instructions per second."

In May, 1955 IBM lost the bid because of this unanticipated change of direction in their proposal. UNIVAC, the dominant computer manufacturer at the time, had won the contract for LARC, now called the Livermore Automatic Research Computer, a decimal computer.

In September, 1955 fearing that Los Alamos might also order a LARC, IBM submitted a preliminary proposal for a high-performance binary computer based on the improved design that Livermore had rejected, which they received with interest. In January, 1956, Project Stretch was formally initiated.

In November, 1956 IBM won the contract for a binary computer with the aggressive performance goal of a "speed at least 100 times the IBM 704" (i.e. 4 MIPS) to the Los Alamos Scientific Laboratory. Delivery was slated for 1960.

During design it proved necessary to reduce the clock speeds, making it clear that Stretch could not meet its aggressive performance goals, but estimates of performance ranged from 60 to 100 times the IBM 704. In 1960, the price of $13.5 million was set for the IBM 7030.

In 1961, actual benchmarks indicated that the performance of the IBM 7030 was only about 30 times the IBM 704 (i.e. 1.2 MIPS), causing considerable embarrassment for IBM. In May, 1961 Tom Watson announced a price cut of all 7030s under negotiation to $7.78 million and immediate withdrawal of the product from further sales.

Its floating-point addition time was 1.38 to 1.5 microseconds, multiplication time was 2.48 to 2.70 microseconds, and division time was 9.00 to 9.90 microseconds;

Technical impact

While the IBM 7030 was not considered successful, it spawned many technologies incorporated in future machines that were highly successful. The Standard Modular System transistor logic was the basis for the IBM 7090 line of scientific computers, the IBM 7080 business computer, the 7040 and 1400 lines, and the IBM 1620 small scientific computer. (The 7030 used about 170,000 transistors.) The IBM 7302 Model I Core Storage units were also used in the IBM 7090 and IBM 7080. Multiprogramming, memory protection, generalized interrupts, the 8-bit byte were all concepts later incorporated in the IBM System/360 line of computers as well as most later CPUs. Instruction pipelining, prefetch and decoding, and memory interleaving were used in later supercomputer designs such as the IBM System/360 Models 91, 95 and 195, and the IBM 3090 series as well as computers from other manufacturers. These techniques are now used in most advanced microprocessors such as the Intel Pentium and the Motorola/IBM PowerPC.

Customer deliveries

Los Alamos Scientific Laboratories (LASL) in April 1961, accepted in May 1961, and used until June 21, 1971.
U.S. National Security Agency in February 1962 as the main CPU of the IBM 7950 Harvest system, used until 1976 when the IBM 7955 Tractor tape system developed problems due to worn cams that could not be replaced.
Lawrence Livermore Laboratory, Livermore, California.
Atomic Weapons Establishment, Aldermaston, England.
U.S. Weather Bureau.
MITRE Corporation, used until August, 1971. In the spring of 1972 it was sold to Brigham Young University.
U.S. Navy Dahlgren Naval Proving Ground.
IBM.
Commissariat à l'Énergie Atomique, France.

Note: The Lawrence Livermore Laboratory's IBM 7030 (except for its core memory) and portions of the MITRE Corporation/Brigham Young University IBM 7030 now reside in the Computer History Museum collection, in Mountain View, California.

Architecture

Data Formats

Fixed point numbers were variable length, stored in either binary (1 to 64 bits) or decimal (1 to 16 digits) and either unsigned format or sign/magnitude format. In decimal format digits were variable length "bytes" (4 to 8 bits).
Floating point numbers had a 1-bit exponent flag, a 10-bit exponent, a 1-bit exponent sign, a 48-bit magnitude, and a 4-bit sign "byte" in sign/magnitude format.
Alphanumeric characters were variable length and could use any character code of 8-bits or less.
"Bytes" were variable length (1 to 8 bits).

Instruction Format

Instructions were either 32-bit or 64-bit.

Registers

The registers overlayed the first 32 addresses of memory, as shown in the table below.

Address	Mnemonic	Register	Stored in:
0	$Z	64-bit Zero	Main Core Storage
1	$IT	19-bit Interval Timer	Index Core Storage
1	$TC	36-bit Time Clock	Index Core Storage
2	$IA	18-bit Interruption Address	Main Core Storage
3	$UB	18-bit Upper Boundary Address	Transistor Register
	$LB	18-bit Lower Boundary Address
		1-bit Boundary Control
4		64-bit Maintanance Bits	Main Core Storage
5	$CA	7-bit Channel Address	Transistor Register
6	$CPUS	19-bit Other CPU Bits	Transistor Register
7	$LZC	7-bit Left Zero count	Transistor Register
7	$AOC	7-bit All Ones count	Transistor Register
8	$L	Left half of 128-bit Accumulator	Transistor Register
9	$R	Right half of 128-bit Accumulator
10	$SB	8-bit Accumulator sign - ZZZZSTUV
11	$IND	64-bit Indicator Register	Transistor Register
12	$MASK	64-bit Mask Register	Transistor Register
13	$RM	64-bit Remainder Register	Main Core Storage
14	$FT	64-bit Factor Register	Main Core Storage
15	$TR	64-bit Transit Register	Main Core Storage
16 ... 31	$X0 ... $X15	64-bit Index Registers (sixteen)	Index Core Storage

The Accumulator and Index registers operated in signed magnitude format.

Memory

16,384 to 262,144 in banks of 16,384 – 64-bit binary words.

The memory was immersion oil-heated/cooled to stabilize its operating characteristics.

Input/Output

External links

IBM hardware | Early computers | Mainframe computers | Supercomputers