__NOTOC__
DDR SDRAM or double-data-rate synchronous dynamic random access memory is a type of memory integrated circuit used in computers. It achieves greater bandwidth than ordinary SDRAM by transferring data on both the rising and falling edges of the clock signal (double pumped). This effectively nearly doubles the transfer rate without increasing the frequency of the front side bus. Thus a 100 MHz DDR system has an effective clock rate of 200 MHz when compared to equivalent SDR SDRAM, the “SDR” being a retrospective designation.
With data being transferred 8 bytes at a time DDR RAM gives a transfer rate of (memory bus clock rate) × 2 (for dual rate) × 8 (number of bytes transferred). Thus with a bus frequency of 100 MHz, DDR-SDRAM gives a max transfer rate of 1600 MB/s.
JEDEC has set standards for speeds of DDR SDRAM, divided into two parts: The first specification is for memory chips and the second is for memory modules.
Note: All RAM speeds in-between or above these listed specifications are not standardized by JEDEC — most often they are simply manufacturer optimizations using higher-tolerance or overvolted chips.
The package sizes in which DDR SDRAM is manufactured are also standardised by JEDEC.
There is no architectural difference between DDR SDRAM designed for different clock frequencies, e.g. PC-1600 (designed to run at 100 MHz) and PC-2100 (designed to run at 133 MHz). The number simply designates the speed that the chip is guaranteed to run at. Hence you can run DDR SDRAM at lower clock speeds than it was made for (underclocking) or higher clock speeds than it was made for (overclocking).
DDR SDRAM DIMMs have 184 pins (as opposed to 168 pins on SDR SDRAM, or, 240 pins on DDR-2), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDR SDRAM has two). DDR operates at a voltage of 2.5 V, compared to 3.3 V for SDR SDRAM. This can significantly reduce power usage.
Many new chipsets use these memory types in dual-channel or even quad channel configurations, which doubles or quadruples the effective bandwidth.
DDR Prefetch buffer width is 2 bits, DDR2 uses 4 bits.
Memory manufacturers have stated that it is impractical to mass-produce DDR1 memory with effective clock rates in excess of 400 MHz. DDR2 picks up where DDR-1 leaves off, and is available at clock rates of 400 MHz and higher.
RDRAM is a particularly expensive alternative to DDR SDRAM, and most manufacturers have dropped its support from their chipsets.
DDR-SDRAM | DDR | DDR SDRAM | DDR SDRAM | DDR SDRAM | DDR SDRAM | DDR SDRAM | DDR SDRAM | DDR SDRAM | DDR SDRAM | DDR SDRAM | DDR SDRAM
This article is licensed under the GNU Free Documentation License.
It uses material from the
"DDR SDRAM".
Home Page • arts • business • computers • games • health • hospitals • home • kids & teens • news • physicians • recreation• reference • regional • science • shopping • society • sports • world